<![CDATA[Digital Electronics - Processor Design]]>Fri, 15 Jan 2016 12:38:35 +0530Weebly<![CDATA[Memory Access]]>Fri, 24 Oct 2014 14:45:31 GMThttp://digitalbyte.weebly.com/processor-design/memory-accessWhy memory access is important aspect?
The statistics* obtained by running some program on ARM processor shows that, around 43% of instructions dynamically executed by the processor are related to the data transfer (to and from memory), while 23% of instructions are related to control flow i.e. to branch to a sub-routine. Only 34% are ALU instructions & other.
Though this statistics are obtained for ARM, similar is case for almost all general-purpose computing applications.

(* reference from book : Steve Furber, "Arm - System-on-chip architecture", 2nd ed, 2000)
So, a processor, which is defined to be a digital thing that 'processes' data, indeed shows most of its performance in moving the data to and form memory.
In this context, the memory access should definitely be considered while designing a processor.

For what purpose does a processor access the memory?
- to fetch an instruction
- to fetch data operands from memory
- to store data result in memory  etc.

The memory mentioned here is either its internal memory (registers) or the external memory connected to processor such as disk/sdCard etc. In case of internal memory, the access time is much low, but access time for external memory is often not negligible, given the fact that almost 40% time of program execution is spent on memory access.

For various kinds of memories connected to a CPU, the speed and capacity hierarchy is as shown in figure below:
Since the registers are available on-chip, their access time is lowest. The main memory (RAM) is frequently accessed by CPU, which is comparatively slower. Thus, a secondary on-chip memory, called CACHE memory is often used in modern processors. The cache stores some data/code which is frequently needed.
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<![CDATA[The MU0 Processor – ALU]]>Mon, 06 Oct 2014 03:55:01 GMThttp://digitalbyte.weebly.com/processor-design/the-mu0-processor-alu From the instruction set of MU0, it may seem like the ALU needs to perform only two operations viz. ADD and SUB. However, the way the datapath is designed, ALU gets some additional responsibilities.

Consider that X and Y are LHS and RHS inputs to ALU respectively, and Z is its output. X bus is accessed by ACC and PC, while Y bus accessed by IR and memory.

Following are the operations supported by MU0 ALU:
1) Addition (ADD instruction)
Z = X+Y
where, X = [ACC] and Y = [memory]

2) Subtraction (SUB instruction)
Z = X-Y.  In this case, the adder can act as subtractor.
The ALU performs
               Z = X+(-Y)              where, X = [ACC] and Y = [memory]

3) Increment PC
After each and every instruction, the PC is incremented by 1.
The ALU performs
               Z = X + 1               where X = [PC]

4) Write to ACC (LDA instruction) and to PC (branch instruction)
The ALU performs               Z = 0 + Y               where Y = [IR]

Each operation can be expressed as an addition operation. This means that ALU contains ADDER and other circuitry to choose the proper operand. The MU0 ALU schematic :

Pre-condition logic is able to reset either of the operands to 0. For various operations, the pre-condition on X-bus and Y-bus, and carry-in are shown below in tabular form:
Instruction Type X bus Y bus Carry-In
ADD as it is as it is 0
SUB as it is ”INVERT” 0
PC increment as it is 0 1
branches 0 as it is 0

In conclusion, we can say that an adder, along with some extra logic is used to create this simple ALU. We'll stop this discussion on MU0 processor here.

Next is what? . . . let's discuss next the things that makes a processor more powerful...

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<![CDATA[The MU0 Processor – Datapath]]>Sun, 05 Oct 2014 16:15:01 GMThttp://digitalbyte.weebly.com/processor-design/the-mu0-processor-datapathThe RTL (Register-Transfer Level) datapath is sketched so as to ensure that every desired operation can be performed. In other words, the datapath is so sketched that internal signals get all necessary paths from register-to-register.

The MU0 datapath
The control signals required by various blocks are not considered in this part.

e.g. The datapath for Arithmetic Operations (ADD, SUB)

Datapath for Fetch stage

Datapath for Decode & Execute stages

Next we discuss the ALU of MU0 processor in details.

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