From the instruction set of MU0, it may seem like the ALU needs to perform only two operations viz. ADD and SUB. However, the way the datapath is designed, ALU gets some additional responsibilities.
Consider that X and Y are LHS and RHS inputs to ALU respectively, and Z is its output. X bus is accessed by ACC and PC, while Y bus accessed by IR and memory.
The RTL (Register-Transfer Level) datapath is sketched so as to ensure that every desired operation can be performed. In other words, the datapath is so sketched that internal signals get all necessary paths from register-to-register.
All the instructions in MU0 processor instruction-set are of fixed-length of 16-bit. First 4 MSBs are the op-code bits which uniquely indicate each instruction while remaining 12 LSBs indicate address of the non-implicit operand.
Articles and stuff addressing the design issues of a digital processor . . .
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