The RTL (Register-Transfer Level) datapath is sketched so as to ensure that every desired operation can be performed. In other words, the datapath is so sketched that internal signals get all necessary paths from register-to-register.
The control signals required by various blocks are not considered in this part.
e.g. The datapath for Arithmetic Operations (ADD, SUB)
Datapath for Fetch stage
Datapath for Decode & Execute stages
Next we discuss the ALU of MU0 processor in details.
Connect with Digital Byte on facebook to get updates.
Articles and stuff addressing the design issues of a digital processor . . .
Like facebook page to get updates :