Register
A register is one which registers/stores/remembers data. Since a flip-flop stores 1-bit data, it is called a 1-bit register. In any practical application, it is required to store large amount of data. So, a practical register stores multi-bit data. E.g. a register could be an 8-bit register. The one shown in diagram below is 4-bit register
(D1 D2 D3 D4) is 4-bit parallel input to the register i.e. using these four lines, we can put 4-bit data into register simultaneously.
(Q1 Q2 Q3 Q4) is parallel output from register i.e. 4-bit data can be retrieved from these lines.
SI is serial input from which data can be entered bit-by-bit while SO is serial output from which data can be retrieved bit-by-bit.
Load input is used to load data parallel while Clear is used to reset all the bits in register to LOW.
Clock facilitates all these operations. Clock could be level or edge triggered depending on design requirements.
Depending on how the input is given and how output is retrieved, there are four modes of operation:
i) Serial In Serial Out (SISO)
ii) Serial In Parallel Out (SIPO)
iii) Parallel In Serial Out (PISO)
iv) Parallel In Parallel Out (PIPO)
(Q1 Q2 Q3 Q4) is parallel output from register i.e. 4-bit data can be retrieved from these lines.
SI is serial input from which data can be entered bit-by-bit while SO is serial output from which data can be retrieved bit-by-bit.
Load input is used to load data parallel while Clear is used to reset all the bits in register to LOW.
Clock facilitates all these operations. Clock could be level or edge triggered depending on design requirements.
Depending on how the input is given and how output is retrieved, there are four modes of operation:
i) Serial In Serial Out (SISO)
ii) Serial In Parallel Out (SIPO)
iii) Parallel In Serial Out (PISO)
iv) Parallel In Parallel Out (PIPO)
Register, using flip-flops:
The clock signal to each FF is given by a single clock source. Since all FFs are negative edge triggered (indicated by bubble at clock signal), at each falling edge of the clock, data is shifted from Q4 to Q3 to Q2 to Q1 i.e. from MSB to LSB. A common ‘clear’ signal is used to reset all FFs simultaneously. A ‘preset enable’ signal is used for loading the data parallel. Output can be obtained in serial or parallel form.
All four modes mentioned above viz. SISO, SIPO, PISO, PIPO are possible with this circuit configuration. However, shifting is possible only from left-to-right. To make it possible to shift data to either left or right, further modifications are needed.
All four modes mentioned above viz. SISO, SIPO, PISO, PIPO are possible with this circuit configuration. However, shifting is possible only from left-to-right. To make it possible to shift data to either left or right, further modifications are needed.
Bidirectional shift-register:
The figure above shows a 4-bit bi-directional shift-register. Each of the flip-flop’s input is connected to both outputs of flip-flops at either side. Left-shift or Right-shift operation is chosen by ‘Mode’ control signal.
For Mode =1, ‘A’ marked AND gates are operative and data is shifted serially to the Right side.
For Mode =0, ‘B’ marked AND gates are operative and data is shifted serially to the Left side.
The preset enable circuitry, not shown in diagram, may be present to load data in parallel. Also, data may be retrieved in parallel at output of each flip-flop.
For Mode =1, ‘A’ marked AND gates are operative and data is shifted serially to the Right side.
For Mode =0, ‘B’ marked AND gates are operative and data is shifted serially to the Left side.
The preset enable circuitry, not shown in diagram, may be present to load data in parallel. Also, data may be retrieved in parallel at output of each flip-flop.