Counter
Counter is another widely used application of flip-flops. It is also a sequential circuit, driven by a clock, which might have some sophistications provided, like load preset value, clear count, up-count/down-count etc.
Counter is simply a circuit that counts events. Event is implicated by a clock signal.
Counter is simply a circuit that counts events. Event is implicated by a clock signal.
The figure above shows basic arrangement of a 4-bit counter. Four T flip-flops are connected in such a way that clock of every next FF is driven by output of previous FF whereas clock of first FF is driven by event pulses to be counted. All T-inputs are tied to logic 1 and each FF is falling edge triggered, meaning that for each falling edge, output of FF toggles.
Waveforms of event pulses and output of each FF are shown below:
Waveforms of event pulses and output of each FF are shown below:
The ‘event pulses’ need not be a periodic wave, because events (like some objects passing over conveyer or people entering a hall) may occur at any time. We assume an event pulse waveform as shown above, which is applied to clock input of first T-FF. At every falling edge of pulses, its output toggles and drives next T-FF’s clock and so on…
Considering output of first T-FF to be LSB and output of last T-FF to be MSB, at some time instances marked t0, t1 . . ., we can find the count. Say, at t4, count is (0100) which is 4 in binary. And actually, 4 events have occurred at that instance. In this way, a 4-bit counter can count from (0000) to (1111) i.e. 16 events and then count rolls-back to (0000) again.
In this circuit, unlike register, clock signal to all FFs is not common. The clock signal ripples through all the FFs. For this reason, this circuit is also termed as an ASYNCHRONOUS or RIPPLE counter.
The drawback of ripple counter is that the output count takes some time to settle down to accurate value until the clock signal passes through all FFs. For large number of FFs in the counter, the delay in propagation might be considerable value. This limits the use of this circuit in high speed applications.
Next is a SYNCHRONOUS counter, in which all FFs are driven by common clock, eliminating the speed limit of asynchronous counter.
Considering output of first T-FF to be LSB and output of last T-FF to be MSB, at some time instances marked t0, t1 . . ., we can find the count. Say, at t4, count is (0100) which is 4 in binary. And actually, 4 events have occurred at that instance. In this way, a 4-bit counter can count from (0000) to (1111) i.e. 16 events and then count rolls-back to (0000) again.
In this circuit, unlike register, clock signal to all FFs is not common. The clock signal ripples through all the FFs. For this reason, this circuit is also termed as an ASYNCHRONOUS or RIPPLE counter.
The drawback of ripple counter is that the output count takes some time to settle down to accurate value until the clock signal passes through all FFs. For large number of FFs in the counter, the delay in propagation might be considerable value. This limits the use of this circuit in high speed applications.
Next is a SYNCHRONOUS counter, in which all FFs are driven by common clock, eliminating the speed limit of asynchronous counter.
Synchronous counter design
The design of synchronous counter emerges from truth-table or state-table of the counter.
From the above table, we can observe that Q1 toggles at each (rising or falling) clock edge; whenever there is ‘1 to 0’ transition on Q1, value of Q2 is toggled; and similarly, for ‘11 to 00’ transition on Q2Q1, value of Q3 is toggled. Thus, T-input of first FF is always tied to logic-1, of second FF is tied to Q1 and of third is tied to AND of (Q1Q2). For 4-bit counter, fourth T-FF’s T inputs would be tied to AND of (Q1Q2Q3). Clock to each FF is common signal, which is pulses to be count.
Such a 4-bit Synchronous counter is shown in diagram below:
Such a 4-bit Synchronous counter is shown in diagram below:
This circuit is designed by observing the state-table. Another approach could be using the K-map to find equations and then design the circuit. We can apply this technique to design a counter with some unusual (not natural-binary) count or counter that counts some specific values only. This is easily possible with synchronous counter.
Another feature that can be added to a counter is UP/DOWN mode control (like LEFT/RIGHT shift control for a shift-register).
Another feature that can be added to a counter is UP/DOWN mode control (like LEFT/RIGHT shift control for a shift-register).