Logic design of any kind, whether combinatorial or sequential, requires various techniques to obtain optimized logic. Basically these involve use of basic laws of boolean algebra and some logical calculations based on them.
A widely used logic optimization technique is K-map reduction technique, as long as variables in logic equations are less enough. This technique is used throughout design examples illustrated on this site. However, K-map reduction technique itself has not been explained on this site. We recommend viewing following NPTEL videos to understand these basics:
