From the instruction set of MU0, it may seem like the ALU needs to perform only two operations viz. ADD and SUB. However, the way the datapath is designed, ALU gets some additional responsibilities.
Consider that X and Y are LHS and RHS inputs to ALU respectively, and Z is its output. X bus is accessed by ACC and PC, while Y bus accessed by IR and memory.
Articles and stuff addressing the design issues of a digital processor . . .
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